CHAPTER 1

INTRODUCTION

A capacitor  is a passive two- terminal electrical component used to store electrical energy temporarily in an electric field. The forms of practical capacitors vary widely, but all contain at least two electrical conductors (plates) separated by a dielectric (i.e. an insulator that can store energy by becoming polarized). The conductors can be thin films, foils or sintered beads of metal or conductive electrolyte, etc. The non-conducting dielectric acts to increase the capacitor's charge capacity. A dielectric can be glass, ceramic, plastic film, air, vacuums, paper, mica, oxide layer etc. Capacitors are widely used as parts of electrical circuits in many common electrical devices. Unlike a resistor, an ideal capacitor does not dissipate energy. Instead, a capacitor stores energy in the form of an electrostatic field between its plates.

1.1 Series-equivalent circuit for Ceramic Capacitor

All electrical characteristics of ceramic capacitors can be defined and specified by a series equivalent circuit composed out of an idealized capacitance and additional electrical components, which model all losses and inductive parameters of a capacitor. In this series-equivalent circuit the electrical characteristics of a capacitors is defined by

 

                                              

• C, the capacitance of the capacitor,

• R insul, the insulation resistance of the dielectric, not to be confused with the insulation of the housing

• RESR, the equivalent series resistance, which summarizes all ohmic losses of the capacitor, usually abbreviated as “ESR”.

• LESL, the equivalent series inductance, which is the effective self-inductance of the capacitor, usually abbreviated as “ESL”.

 

 

1.1.1 Capacitance standard values and tolerance

The “rated capacitance” CR or “nominal capacitance” CN is the value for which the capacitor has been designed. The actual capacitance depends on the measuring frequency and the ambient temperature. Standardized conditions for capacitors are a low-voltage AC measuring method at a temperature of 20 °C with frequencies of

• Class 1 ceramic capacitors

  CR ≤ 100 pF at 1 MHz, measuring voltage 5 V

  CR> 100 pF at 1 kHz, measuring voltage 5 V

• Class 2 ceramic capacitors

  CR ≤ 100 pF at 1 MHz, measuring voltage 1 V

  100 pF < CR ≤ 10 µF at 1 kHz, measuring voltage 1 V

  CR> 10 µF at 100/120 Hz, measuring voltage 0.5 V

Capacitors are available in different, geometrically increasing preferred values as specified in the E series standards specified in IEC/EN 60063. According to the number of values per decade, these were called the E3, E6, E12, E24, etc. series. The units used to specify capacitor values includes everything from picofarad (pF), nano-farad(nF), microfarad (µF) and farad (F).The percentage of allowed deviation of the capacitance from the rated value is called capacitance tolerance. The actual capacitance value must be within the tolerance limits, or the capacitor is out of specification.

 

1.2 Transistor BC 548 

The BC548 is a general purposen-p-n bipolar junction transistor found commonly in European electronic equipment and present-day designs in Australian and British electronics magazines where a commonly-available low-cost n-p-n transistor is required. It is a part of a family of NPN and PNP epitaxial silicon transistors that include higher-quality variants, originating in 1966 when Philips introduced the metal-cased BC108 family of transistors which became the most used transistors in Australia and taken up by many European manufacturers.. The BC548 is low cost and is available in most European Union and many other countries. It is often the first type of bipolar transistor hobbyist’s encounter, and is often featured in designs in hobby electronics magazines where a general        

 

Figure 1.2  Identifying terminals in transistor BC548

purpose transistor is required. The type number of any of the devices in this "family" may be followed by a letter to indicate a narrow range of gain ( ) spread (although it is not so common for a BCxx7 or BCxx8 part to be available with a "C" gain grouping). So a BC548 might have a current gain anywhere between 110 and 800, but the gain of a BC548A would be within the range of 110 to 220.

• "A" indicates low gain (110 to 220 at 2 mA),

• "B" indicates medium gain (200 to 450).

• "C" indicates high gain (420 to 800).

1.2.1 Specifications

• Devices registered to this Pro Electron number must have minimum performance characteristics.

• Breakdown voltage, collector-to-emitter with base open-circuit VCEO = 30 V (see below)

• Rated continuous collector current IC = 100 mA(Fairchild's BC548 at one time had a higher rating)

• Rated total power dissipation Ptotal = 500 mW(some manufacturers may specify 625 mW - see below)

• Transition frequency (gain-bandwidth product) ft = 150 MHz minimum (300 MHz typical)

1.2.2 Power Ratings

The rated power dissipation for transistors is the total power developed across both junctions of the transistor that will raise the internal temperature to the maximum permitted (i.e. not something that should be maintained in normal use), and will be specified for a given ambient temperature for low-power transistors such as these, in this case 25 degrees Celsius. In practice factors such as the proximity of the transistor to the printed circuit board will influence how well heat can be removed from the transistor and proximity to other heat-generating components will increase the ambient temperature - and probably reduce the permissible dissipation below the    500-625 mW ideal-conditions specification.

1.2.3 Voltage ratings   

The BC548 and BC549, and their PNP counterparts (BC558 and BC559) can be used in circuits where voltages reach no more than 30 Volts, limited mainly by their VCEO rating. The VCBO rating refers to the maximum voltage between collector and base with the emitter open-circuit (not typical operation), and their predecessors, the BC108 and BC109, while having VCBO or VCES ratings of 30 V have only a 20 VCEO) rating, meaning a BC548 (or BC549) can replace a BC108 but a BC108 might not be a safe replacement for a BC148.

1.3  Light Emitting Diodes(LED)

The light-emitting diode (LED) is a two-lead semiconductor light source. It is a p–n junction diode, which emits light when activated.[4] When a suitable voltage is applied to the leads, electrons are able to recombine with electron holes within the device, releasing energy in the form of photons. This effect is called electroluminescence, and the color of the light (corresponding to the energy of the photon) is determined by the energy band gap of the semiconductor. An LED is often small in area (less than 1 mm2) and integrated optical components may be used to shape its radiation pattern. Efficiency droop is the decrease in luminous efficacy of LEDs as the electric current increases above tens of mill amperes. This effect was initially theorized to be related to elevated temperatures. Scientists proved the opposite to be true that, although the life of an LED would be shortened, the efficiency droop is less severe at elevated temperatures . Instead of increasing current levels, luminance is usually increased by combining multiple LEDs in one bulb. Solving the problem of efficiency droop would mean that household LED light bulbs would need fewer LEDs, which would significantly reduce costs. Researchers have found a way to lessen the efficiency droop. They found that the droop arises from non-radiative Auger recombination of the injected carriers. They created quantum wells with a soft confinement potential to lessen the non-radiative Auger processes. The higher thermal conductivity reduces self-heating effects. This effect was initially theorized to be related to elevated temperatures. Scientists proved the opposite to be true that, although the life of an LED would be shortened, the efficiency droop is less severe at elevated temperatures. The mechanism causing efficiency droop was identified in 2007 as Auger recombination, which was taken with mixed reaction. In 2013, a study identified Auger recombination as the cause of efficiency droop. In addition to being less efficient, operating LEDs at higher electric currents creates higher heat levels which compromise the lifetime of the LED. Because of this increased heating at higher currents, high-brightness LEDs have an industry standard of operating at only 350 mA, which is a compromise between light output, efficiency.

1.4 Piezo Buzzer

It is the handy sound generator used in electronic circuits to give audio indication .It is widely used as alarm generator in electronic devices. It is available in various types and size to suit the requirements. A piezo buzzer has a piezo disc and an oscillator inside. When the buzzer is powered, the oscillator generates a frequency

Figure 1.3  Internal view of piezo buzzer

around 2-4 kHz and the Piezo element vibrates accordingly to produce the sound. An ordinary piezo buzzer works between  3 – 12 volts DC.

Working of the piezo element

Piezoelectricity is the ability of some materials (notably crystals and ceceramics, including bone) to generate an electric field or electric potential[1] in response to applied mechanical stress. The effect is closely related to a change of polarization density within the material's volume. If the material is not short-circuited, the applied stress induces a voltage across the material. The word is derived from the Greek piezo or piezein, which means to squeeze or press. The word "buzzer" comes from the rasping noise that buzzers made when they were electromechanical devices, operated from stepped-down AC line voltage at 50 or 60 cycles. Other sounds commonly used to indicate that a button has been pressed are a ring or a beep. Piezo element is a circular shaped metal plate with a thin coating of Piezo material. The piezomaterial used is Lead zirconate Titanate . This material exhibits both Direct and Indirect piezoelectric property. Indirect piezoelectric property is the vibration of the piezoelectric crystals in the presence of an electric field. The piezoelectric crystals also show direct piezoelectric property in which a mechanical stress like vibration or application of heat generates around 1-2 volts in the piezoelement. The white piezo material coating is Positive while the rim of the element is Negative. Oscillator circuit inside the buzzer consists of an Inductor, a transistor, capacitors and resistors. When the oscillator circuit gets 3-12 volt DC, The transistor, Inductor combination oscillates which are fed to the Piezo crystals and the crystals and the plate vibrate according to the frequency. In order to give resonance, the rim of the element is glued to a plastic case so that the plate can vibrate freely. The oscillation in the Piezo buzzer is between 2 – 4 kHz. This sound is piercing because our hearing threshold is maximum in this frequency. Buzzer uses this frequency to get easy attention even in a highly noisy environment. Buzzers are used as alarms so this frequency is necessary. Piezo element is prone to weather changes and aging. The piezoelectric property may deteriorate due to aging and the buzzer may fail to work. The Piezo material is coated as a thin film so that during soldering, the wire along with the piezo material may detach. Once a portion of the Piezo material is detached, that element cannot be used. So always use very thin wire and apply solder only once. Overheating may damage the piezo material. If it is stored, use a plastic cover and keep it in a place free from moisture and heat.

1.5 Selection of antenna

The antenna realized in this project is loop antenna. Loop antennas should never be used as transmitting antennas because of  low directivity. It is always a good choice to select a loop antenna as a receiving antenna. In the present case the leads of 0.22µF capacitor will act as inductance.   

Parallel Line Inductance

Figure 1.4 Leads of Capacitor acting as parallel line inductance

                                                                                                    1.1

                                                                                 1.2

a = wire radius; l = wire length parallel to ground plane ;h = height of wire above ground plane to bottom of wire.

Electrical equivalent circuit of loop antenna

           The below circuit diagram is the    equivalent  circuit diagram of loop antenna. The circuit has resemblance with the mobile bug circuit diagram. Here in this case the value of   C1 is equal to 0.22µF,R1 is the input impedance of the circuit   and the value of inductance is calculated from the equation (1.1).

 

Figure 1.5 Electrical equivalent circuit of loop antenna.

 

 

 

 

 

 

 

 

 

 

 

 

 

CHAPTER 2

555 TIMERS AND OPAMP CA3130

 2.1 Design Considerations in using   555 Timer

The timer will operate over a guaranteed voltage range of 4.5V to 15VDC with 16VDC being the absolute maximum rating. Most of the devices, however, will operate at voltage levels as low as 3VDC. The timing interval is independent of supply voltage since the charge rate and threshold level of the comparator are both directly proportional to supply. The supply voltage may be provided by any number of sources, however, several precautions should be taken. The most important, the one which provides the most headaches if not practiced, is good power supply filtering and adequate bypassing. Ripple on the supply line can cause loss of timing accuracy. The threshold level shifts, causing a change of charging current. This will cause a timing error for that cycle.

Due to the nature of the output structure, a high power totem-pole design, the output of the timer can exhibit large current spikes on the supply line. Bypassing is necessary to eliminate this phenomenon. A capacitor across the VCC and ground, directly across the device, is necessary and ideal. The size of a capacitor will depend on the specific application. Values of capacitance from 0.01mF to 10mF are not uncommon, but note that the bypass capacitor would be as close to the device as physically possible.

 

Table 2.1 Description of pins in IC 555 Timer

Pin

Name

Purpose

1

GND

Ground reference voltage, low level (0 V)

2

TRIG

The OUT pin goes high and a timing interval starts when this input falls below 1/2 of CTRL voltage (which is typically 1/3 VCC, CTRL being 2/3 VCC by default if CTRL is left open).

3

OUT

This output is driven to approximately 1.7 V below +VCC, or to GND.

4

RESET

A timing interval may be reset by driving this input to GND, but the timing does not begin again until RESET rises above approximately 0.7 volts. Overrides TRIG which overrides THR.

5

CTRL

Provides "control" access to the internal voltage divider (by default, 2/3 VCC).

6

THR

The timing (OUT high) interval ends when the voltage at THR ("threshold") is greater than that at CTRL (2/3 VCC if CTRL is open).

7

DIS

Open collector output which may discharge a capacitor between intervals. In phase with output.

8

VCC

Positive supply voltage, which is usually between 3 and 15 V depending on the variation.

 

These specifications apply to the NE555. Other 555 timers can have different specifications depending on the grade (military, medical, etc.).The standard 555 package includes 25 transistors, 2 diodes and 15 resistors on a silicon chip installed in an 8-pin mini dual-in-line package (DIP-8)

Table 2.2  Maximum operating conditions of IC 555 Timer

Supply voltage (VCC)

4.5 to 15 V

Supply current (VCC = +5 V)

3 to 6 mA

Supply current (VCC = +15 V)

10 to 15 mA

Output current (maximum)

200 mA

Maximum Power dissipation

600 mW

Power consumption (minimum operating)

30 mW@5V, 225 mW@15V

Operating temperature

0 to 60°C

 

Pin 1 (Ground) The ground (or common) pin is the most-negative supply potential of the device, which is normally connected to circuit common (ground) when operated from positive supply voltages.
Pin 2 (Trigger):  This pin is the input to the lower comparator and is used to set the latch, which in turn causes the output to go high. This is the beginning of the timing sequence in monostable operation. Triggering is accomplished by taking the pin from above to below a voltage level of 1/3 V+ (or, in general, one-half the voltage appearing at pin 5). The action of the trigger input is level-sensitive, allowing slow rate-of-change waveforms, as

                                              Figure 2.1 Identification of  pins in 555 Timer

well as pulses, to be used as trigger sources. The trigger pulse must be of shorter duration than the time interval determined by the external R and C. If this pin is held low longer than that, the output will remain high until the trigger input is driven high again. One precaution that should be observed with the trigger input signal is that it must not remain lower than 1/3 V+ for a period of time longer than the timing cycle. If this is allowed to happen, the timer will re-trigger itself upon termination of the first output pulse. Thus, when the timer is driven in the monostable mode with input pulses longer than the desired output pulse width, the input trigger should effective be shortened by differentiation. The minimum-allowable pulse width for triggering is somewhat dependent upon pulse level, but in general if it is greater than the 1uS (micro-Second), triggering will be reliable. A second precaution with respect to the trigger input  concerns storage time in the lower comparator. This portion of the circuit can exhibit normal turn-off delays of several microseconds after triggering; that is, the latch can still have a trigger input for this period of time after the trigger pulse. In practice, this means the minimum monostable output pulse width should be in the order of 10uS to prevent possible double triggering due to this effect. The voltage range that can safely be applied to the trigger pin is between V+ and ground. A dc current, termed the trigger current, must also flow from this terminal into the external circuit. This current is typically 500nA  (nano-amp) and will define the upper limit of resistance allowable from pin 2 to ground. For an  astable   configuration operating at v = 5 volts, this resistance is 3 Mega-ohm; it can be greater for higher V+ levels.
Pin 3 (Output):  The output of the 555 comes from a high-current totem-pole stage made up of transistors        Q20 - Q24. Transistors Q21 and Q22 provide drive for source-type loads, and their Darlington connection provides a high-state output voltage about 1.7 volts less than the V+ supply level used. Transistor Q24 provides current-sinking capability for low-state loads referred to V+ (such as typical TTL inputs). Transistor Q24 has a low saturation voltage, which allows it to interface directly, with good noise margin, when driving current-sinking logic. Exact output saturation levels vary markedly with supply voltage, however, for both high and low states. At a V+ of 5 volts, for instance, the low state Vce (sat) is typically 0.25 volts at 5 mA.Operating at 15 volts however it can sink 200mA if an output-low voltage level of 2 volts is allowable (power dissipation should be considered in such a case, of course). High-state level is typically 3.3 volts at V+ = 5 volts; 13.3 volts at V+ = 15 volts. Both the rise and fall times of the output waveform are quite fast, typical switching times being 100nS. The state of the output pin will always reflect the inverse of the logic state of the latch, and this fact may be seen by examining. Since the latch itself is not directly accessible, this relationship may be best explained in terms of latch input trigger conditions. To trigger the output to a high condition, the trigger input is momentarily taken from a higher to a lower level. [see "Pin 2 - Trigger"]. This causes the latch to be set and the output to go high. Actuation of the lower comparator is the only manner in which the output can be placed in the high state. The output can be returned to a low state by causing the threshold to go from a lower to a higher level.                       

Pin 4 (Reset):  This pin is also used to reset the latch and return the output to a low state. The reset voltage threshold level is 0.7 volt, and a sink current of 0.1mA from this pin is required to reset the device. These levels are relatively independent of operating V+ level; thus the reset input is TTL compatible for any supply voltage. The reset input is an overriding function; that is, it will force the output to a low state regardless of the state of either of the other inputs. It may thus be used to terminate an output pulse prematurely, to gate oscillations from "on" to "off", etc. Delay time from reset to output is typically on the order of 0.5 µS, and the minimum reset pulse width is 0.5 µS. Neither of these figures is guaranteed, however, and may vary from one manufacturer to another. In short, the reset pin is used to reset the flip-flop that controls the state of output pin 3. The pin is activated when a voltage level anywhere between 0 and 0.4 volt is applied to the pin. The reset pin will force the output to go low no matter what state the other inputs to the flip-flop are in.

Pin 5 (Control Voltage):  This pin allows direct access to the 2/3 V+ voltage-divider point, the reference level for the upper comparator. It also allows indirect access to the lower comparator, as there is a 2:1 divider (R8 - R9) from this point to the lower-comparator reference input, Q13. Use of this terminal is the option of the user, but it does allow extreme flexibility by permitting modification of the timing period, resetting of the comparator, etc. When the 555 timer is used in a voltage-controlled mode, its voltage-controlled operation ranges from about 1 volt less than V+ down to within 2 volts of ground (although this is not guaranteed). Voltages can be safely applied outside these limits, but they should be confined within the limits of V+ and ground for reliability. By applying a voltage to this pin, it is possible to vary the timing of the device independently of the RC network. The control voltage may be varied from 45 to 90% of the Vcc in the monostable mode, making it possible to control the width of the output pulse independently of RC. When it is used in the astable mode, the control voltage can be varied from 1.7V to the full Vcc. Varying the voltage in the astable mode will produce a frequency modulated (FM) output. In the event the control-voltage pin is not used, it is recommended that it be bypassed, to ground with a capacitor of about 0.01uF (10nF) for immunity to noise, since it is a comparator input.

Pin 6 (Threshold):  Pin 6 is one input to the upper comparator (the other being pin 5) and is used to reset the latch, which causes the output to go low. Resetting via this terminal is accomplished by taking the terminal from below to above a voltage level of 2/3 V+ (the normal voltage on pin 5). The action of the threshold pin is level sensitive allowing slow rate-of-change waveforms. The voltage range that can safely be applied to the threshold pin is between V+ and ground. A dc current, termed the threshold current, must also flow into this terminal from the external circuit. This current is typically 0.1µA, and will define the upper limit of total resistance allowable from pin 6 to V+. For either timing configuration operating at V+ = 5 volts, this resistance is 16 Mega-ohm.

Pin 7 (Discharge):  This pin is connected to the open collector of a npn transistor (Q14), the emitter of which goes to ground, so that when the transistor is turned "on", pin 7 is effectively shorted to ground. Usually the timing capacitor is connected between pin 7 and ground and is discharged when the transistor turns "on". The conduction state of this transistor is identical in timing to that of the output stage. It is "on" (low resistance to ground) when the output is low and "off" (high resistance to ground) when the output is high. In both the monostable and astable time modes, this transistor switch is used to clamp the appropriate nodes of the timing network to ground. Saturation voltage is typically below 100mV (millivolt) for currents of 5 mA or less, and off-state leakage is about 20nA (these parameters are not specified by all manufacturers, however). Maximum collector current is internally limited by design, thereby removing restrictions on capacitor size due to peak pulse-current discharge.

Figure 2.2   Internal block diagram of IC 555 Timer

 Pin 8 (V +):  The V+ pin (also referred to as Vcc) is the positive supply voltage terminal of the 555 timer IC. Supply voltage operating range for the 555 is +4.5 volts (minimum) to +16 volts (maximum), and it is specified for operation between +5 volts and +15 volts. The device will operate essentially the same over this range of voltages without change in timing period. Actually, the most significant operational difference is the output drive capability, which increases for both current and voltage range as the supply voltage is increased.

2.2 OPERATIONAL AMPLIFIER CA3130

IC is a 15 MHz Bi MOS Operational amplifier with MOSFET inputs and Bipolar output. The inputs contain MOSFET transistors to provide very high input impedance and very low input current as low as 10pA. It has high speed of performance and suitable for low input current applications.

2.2.1 Description of Operational amplifier

• CA3130A and CA3130 are op amps that combine the MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input advantage of both CMOS and bipolar transistors. Gate protected P-Channel current , and exceptional speed performance. The use of PMOS transistors in the input   stage results in common-mode input-voltage capability down to0.5V below the negative-supply terminal, an important attribute in single-supply applications.

• A CMOS transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit.

 

• The CA3130 Series circuits operate at supply voltages ranging from 5V to 16V. They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications

• Terminal provisions are also made to permit   strobing  of the output stage. The CA3130A offers superior input characteristics over those of the CA3130

 

Figure 2.3   Pin configuration of operational amplifier CA3130

MOSFET Input Stage Provides:

• Very High ZI = 1.5 T

• Very Low current =5pecoamperes at 15V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input    Terminals can be Swung 0.5VBelow Negative Supply Rail

 

 

• Circuit Description

The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in manyapplications. Consequently, the CA3130 Series circuits are ideal for single-supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6essentially rises to the positive supply-rail potential atterminal 7.

Input Stage
 The circuit of the CA3130 is shown in the schematic diagram. It consists of a differential-input stage using PMOS field-effect  transistors (Q6, Q7) working into a mirror-pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6.The mirror-pair transistors also function as a differential-to single ended converter to provide base drive to the second stage bipolar transistor (Q11). Offset  nulling, when desired, can be effected by connecting a 100,000Ω  potentiometer across Terminals 1 and 5 and the potentiometer slider

 

Figure 2.4 Internal block diagram of Operational Amplifier CA3130

 

arm to Terminal 4.Cascade-connected PMOS transistors Q2, Q4 are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described. The small diodes D5 through D8 provide gate-oxide protection against high voltage transients, including static electricity during handling for Q6 and Q7.

Second-Stage

Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor Q11and its cascade-connected load resistance provided by PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A47pF capacitor provides sufficient compensation for stable unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, somewhat above 8.3V, resistor R2and zener diode Z1 serve to establish a voltage of 8.3V across the series-connected circuit, consisting of resistor R1, diodesD1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate-bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode-connected PMOS transistor Q1 with respect to Terminal7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is “mirror-connected (see Note 8)” to both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be identical, the approximately 200μA current in Q1establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series connected R1, D1-D4, and Q1varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply-voltage variations. This variation results in deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance.

Output Stage

The output stage consists of a drain-loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within milli- volts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail. Typical op amp loads are readily driven by the output stage. Because large signal excursions are non-linear, requiring feedback for good waveform reproduction, transient delays may been countered. As a voltage follower, the amplifier  can achieve 0.01% accuracy levels, including the negative supply rail.

 

 

 

 

 

CHAPTER 3

OVERVIEW OF MOBILE BUG

This project consists of IC CA3130 operational amplifier, IC NE 555 monostable multi-vibrator and Buzzer. Mobile transmission data detector can sense the presence of an activated mobile phone from a distance of one and half meters. The circuit can detect the incoming and outgoing calls, SMS and video transmission even if the mobile phone is kept in the silent mode. The moment the bug detects RF transmission signal from an activated mobile phone, it starts sounding a beep alarm and the LED blinks. The alarm continues until the signal transmission ceases.

3.1 MONOSTABLE MULTIVIBRATOR

In the monostable multivibrator, the one resistive-capacitive network is replaced by a resistive network (just a resistor). The circuit can be thought as a half stable multivibrator. Q2 collector voltage is the output of the circuit (in contrast to the astable circuit, it has a perfect square waveform since the output is not loaded by the

                                Figure 3.1  Construction of basic  monostable multivibrator using  BJT

capacitor). Basic animated interactive BJT bistable multivibrator circuit. When triggered by an input pulse, a monostable multivibrator will switch to its unstable position for a period of time, and then return to its stable state. The time period monostable multivibrator remains in unstable state is given by ln(2)R2C1.For the circuit shown, in the stable state Q1 is turned off and Q2 is turned on. It is triggered by zero or negative input signal applied to Q2 base (with the same success it can be triggered by applying positive input signal through a resistor to Q1 base). As a result, the circuit goes in State 1 described above. After elapsing the time, it returns to its stable initial state.

 

WORKING OF 555 TIMER AS A MONOSTABLE MULTIVIBRATOR

The 555 timer  shown here used in its utmost basic mode of operation; as a triggered monostable. One immediate observation is the extreme simplicity of this circuit. Only two components to make up a timer, a capacitor and a resistor. And for noise immunity maybe a capacitor on pin 5. Due to the internal latching mechanism of the 555, the timer  will always time-out once triggered, regardless of any subsequent noise (such as bounce) on the input trigger (pin 2). This is a great asset in interfacing the 555 with noisy sources. Just in case you don't know what 'bounce' is: bounce is a type of fast, short term noise caused by a switch, relay, etc. and then picked up by the input pin. The trigger input is initially high (about 1/3 of +V). When a negative-going trigger pulse is applied to the trigger input (see fig. 9a), the threshold on the lower comparator is exceeded. The lower comparator, therefore, sets the flip-flop. That causes T1 to cut off, acting as an open circuit. The setting of the flip-flop also causes a positive-going output level which is the beginning of the output timing pulse.

 

Figure 3.2 Configuration of  IC 555 Timer  as a monostable  multivibrator

The capacitor now begins to charge through the external resistor. As soon as the charge on the capacitor equal 2/3 of the supply voltage, the upper comparator triggers and resets the control flip-flop. That terminates the output pulse which switches back to zero. At this time, T1 again conducts thereby discharging the capacitor. If a negative-going pulse is applied to the reset input while the output pulse is high, it will be terminated immediately. Whenever a trigger pulse is applied to the input, the 555 will generate its single-duration output pulse. Depending upon the values of external resistance and capacitance used, the output timing pulse may be adjusted from approximately one millisecond to as high as on hundred seconds. For time intervals less than approximately         1-millisecond, it is recommended that standard logic one-shots designed for narrow pulses be used instead of a555 timer. In this application, the duration of output pulse in seconds is approximately equal to:

                                                                                 3.1

The monostable continues to output its pulse regardless of the inputs swing back up. That is because the output is only triggered by the input pulse, the output actually depends on the capacitor charge.
The output pulse width is defined by the above formula and with relatively few restrictions, timing components R(t) and C(t) can have a wide range of values. There is actually no theoretical upper limit on T (output pulse width), only practical ones. The lower limit is 10uS. You may consider the range of T to be 10uS to infinity bounded only by R and C limits. Special R(t) and C(t) techniques allow for timing periods of days, weeks, an even months if so desired. However, a reasonable lower limit for R(t) is in the order of about 10Kilo ohm, mainly from the standpoint of power economy. (Although R(t) can be lower that 10K without harm, there is no need for this from the standpoint of achieving a short pulse width.) A practical minimum for C(t) is about 95pF; below this the stray effects of capacitance become noticeable, limiting accuracy and predictability. Since it is obvious that the product of these two minimums yields a T that is less the 10uS, there is much flexibility in the selection of R(t)and C(t). Usually C(t) is selected first to minimize size (and expense); then R(t) is chosen.
The upper limit for R(t) is in the order of about 15 Mega ohm but should be less than this if all the accuracy of which the 555 is capable is to be achieved. The absolute upper limit of R(t) is determined by the threshold current plus the discharge leakage when the operating voltage is +5 volt. For example, with a threshold plus leakage current of 120nA, this gives a maximum value of 14M for R(t) (very optimistic value). Also, if the C(t) leakage current is such that the sum of the threshold current and the leakage current is in excess of 120 nA the circuit will never time-out because the upper threshold voltage will not be reached. Therefore, it is good practice to select a value for R(t) so that, with a voltage drop of 1/3 V+ across it, the value should be 100 times more, if practical.
So, it should be obvious that the real limit to be placed on C(t) is its leakage, not it's capacitance value, since larger-value capacitors have higher leakages as a fact of life. Low-leakage types, like tantalum or NPO, are available and preferred for long timing periods. Sometimes input trigger source conditions can exist that will necessitate some type of signal conditioning to ensure compatibility with the triggering requirements of the      555. This can be achieved by adding another capacitor, one or two resistors and a small signal diode to the input to form a pulse differentiator to shorten the input trigger pulse to a width less than 10usec. Their values and criterion are not critical; the main one is that the width of the resulting differentiated pulse (after C) should be less than the desired output pulse for the period of time it is below the 1/3 V+ trigger level.

3.2   CA 3130 Operational Amplifier as Current to Voltage Converter

In electronics, a transimpedance amplifier, (TIA) is a current-to-voltage converter, most often implemented using an operational amplifier. The TIA can be used to amplify the current output of sensors to a usable voltage. Current-to-voltage converters are used with sensors that have a current response that is more linear than the voltage response. The transimpedance amplifier presents a low impedance to the  detection circuit   and isolates it from the output voltage of the operational amplifier. In its simplest form a transimpedance amplifier has just a large valued feedback resistor, Rf. The gain of the amplifer is set by this resistor and because the amplifier is
in an inverting configuration, has a value of -Rf.

 

  Figure 3.3 IC CA 3130 working as current to voltage converter

There are several different   configurations  of  transimpedance  amplifiers,  each  suited to a particular application. The one factor they all have in common is the requirement to convert the low-level current of a sensor to a voltage. The gain, bandwidth, as well as current and voltage offsets change with different types of sensors, requiring different configurations of transimpedance   amplifiers . The frequency response of a transimpedance amplifier is inversely proportional to the gain set by the feedback resistor. The product of the gain, Vin/Vo, is very close to being a constant for any given op amp. The sensors that transimpedance amplifiers are used with usually have more capacitance than an op amp can handle. This capacitance across the input terminals of the operational   amplifier, which includes the internal capacitance of the op amp, introduces a low-pass filter in the feedback path. The low pass response of this filter can be characterized as the feedback factor β, which attenuates the feedback signal. This places a greater demand on the amplifier gain.

3.3   Working of Mobile Bug Circuit  

An ordinary RF detector using tuned LC circuits is not suitable for detecting signals in the GHz frequency band used in mobile phones. The transmission frequency of mobile phones ranges from 0.9 to 3 GHz with a wavelength of 3.3 to 10 cm. So a circuit detecting gigahertz signals is required for a mobile bug. Here the circuit uses a 0.22µF disk capacitor (C3) to capture the RF signals from the mobile phone. The lead length of the capacitor is fixed as 18 mm with a spacing of 8 mm between the leads to get the desired frequency. The disk capacitor along with the leads acts as a small gigahertz loop antenna to collect the RF signals from the mobile phone.Op-amp IC CA3130 (IC1) is used in the circuit as a current-to-voltage converter with capacitor C3 connected between its inverting and non-inverting inputs. It is a CMOS version using gate-protected p-channel MOSFET transistors in the input to provide very high input impedance, very low input current and very high speed of performance. The output CMOS transistor is capable of swinging the output voltage to within 10 mV of either supply voltage terminal. Capacitor C3 in conjunction with the lead inductance acts as a transmission line that intercepts the signals from the mobile phone. This capacitor creates a field, stores energy and transfers the stored energy in the form of minute current to the inputs of IC1. This will upset the balanced input of IC1 and convert the current into the corresponding output voltage. Capacitor C4 along with high-value resistor R1 keeps the non-inverting input stable for easy swing of the output to high state. Resistor R2 provides the discharge path for capacitor C4. Feedback resistor R3 makes the inverting input high when the output becomes high. Capacitor C5 (47pF) is connected across ‘strobe’ (pin 0 and ‘null’ inputs (pin 1) of IC1 for phase compensation and gain control to optimize the frequency response. When the mobile phone signal is detected by C3, the output of IC1 becomes high and low alternately according to the frequency of the signal as indicated by LED1.  

         This triggers  monostable timer IC2 through capacitor C7. Capacitor C6 maintains the base bias of transistor T1 for fast switching action. The low-value timing components R6 and C9 produce very short time delay to avoid audio nuisance. Mobile phone uses RF with a wavelength of 30cm at 872 to 2170 MHz .That is the signal is high

                                 

Figure 3.4 Circuit diagram for mobile bug

Frequency   with huge energy. When the mobile phone is active, it transmits the signal in the form of sine wave which passes through the space. Ordinary LC circuits cannot detect high frequency waves near the microwave region. Hence in the circuit, a capacitor is used to detect RF from mobile phone considering that, a capacitor can store energy even from an outside source and oscillate like LC circuit.

3.3.1   Significance of 0.22µF capacitor

A capacitor has two electrodes separated by a ‘dielectric’ like paper, mica etc. The non-polarized disc capacitor is used to pass AC and not DC. Capacitor can store energy and pass AC signals during discharge. 0.22µF capacitor is selected because it is a low value one and has large surface area to accept energy from the mobile radiation. To detect the signal, the sensor part should be like an aerial. So the capacitor is arranged as a mini loop aerial (similar to the dipole antenna used in TV).In short with this arrangement, the capacitor works like an air core coil with ability to oscillate and discharge current.

3.3.2   Radio Frequency Sensing Mechanism by the Capacitor 0.22µF

One lead of the capacitor gets DC from the positive rail and the other lead goes to the negative input of IC1. So the capacitor gets energy for storage. This energy is applied to the inputs of IC1 so that the inputs of IC are almost balanced with 1.4 volts. In this state output is zero. But at any time IC can give a high output if a small current is induced to its inputs. There a natural electromagnetic field around the capacitor caused by the 50Hz from electrical wiring. When the mobile phone radiates high energy pulsations, capacitor oscillates and release energy in the inputs of IC. This oscillation is indicated by the flashing of the LED and beeping of Buzzer. In short, capacitor carries energy and is in an electromagnetic field. So a slight change in field caused by the RF from phone will disturb the field and forces the capacitor to release energy.

 

 

 

 

 

 

 

 

 

 

 

CHAPTER 4

PCB LAYOUT DESIGN AND FABRICATION

PCB Lay Out Design Using PCB  123 Software

After all the components placed on the board, some rules are need to setup special some nets. These include.

4.1  Plane Layer Nets

 If you have plane layers, you will need to establish which nets are tied to the planes. You can navigate to the nets in the Object Hierarchy or graphically select the nets and use RMB Properties to get to the Net Properties Dialog. Assuming you have already identified at least one inner layer as a plane layer you can click on the plane layer checkboxes in the net properties dialog. This tells the system that as soon as a pin connects to a plane layer either because it is a thru-hole pin, it is routed to another thru-hole pin or via, then it is considered connected. If you have multiple nets assigned to the same plane layer you will have to isolate the pins from each net by adding a poly line that encompasses just the pins of one of the plane nets. This has to be done manually. 

• Special Net Widths: Depending on the copper weight of the board, the default width of nets will be either .007‖ or .012‖. This may not be adequate for certain nets, especially those that may be carrying higher current. You can set the line width for these nets in Net Properties Dialog. 

• Special Net Spacing: Depending on the copper weight of the board, the default spacing for nets will be either .007‖ or .012‖. This may not be adequate for certain nets, especially those that may be carrying a high potential and need to meet regulatory requirements or nets that are edge sensitive and need to ensure minimal coupling. You can set the net spacing in the Net Properties Dialog. 

• Routing the board:  After all the components placed on the board, your next task is to route all the nets. There are many factors to consider and there are many tools to help. Generally, you want each layer to have a preferred routing direction or   flow   . Too much meandering on a layer most likely will cut off routing channels before all the routing is complete. For general routing, you have several options available are:

  Auto route : This may be an acceptable solution on sparse to moderately dense designs or designs that have very good connection   flow  to them. On dense boards, running the auto router can be beneficial in determining trouble spots on the board. The auto router settings can be modified in the User Preferences Dialog.

  Partial Auto route: Select a connection or group of connections, right-click the mouse, and select Auto route from the context menu. This will engage the auto router for just those connections. 

  Pin-To-Pin Manual Routing:  If you started your design with a net list then you can just click on a connection (ratline) and start digitizing corners. Because there is knowledge of where the connection terminates you can double click at anytime and the system will automatically finish routing the connection using a straight line or an orthogonal pair of lines. This type of auto-finish does not avoid obstacles and may produce DRC markers. 

  Freestyle Manual Routing: Using the Freestyle tool you can freely insert routes from pins and other routes. You can even define new connectivity this way. There is no auto-finish because there is no end-point defined. The route is terminated by pressing the escape key (leaving a dangling end) or by routing to another pin or route.  For manual routing, there are two broad strategies. One of them is intuitive and the other is less intuitive but can be a very powerful technique on dense designs.

  Complete each Connection, one at a time: this is an obvious technique that involves selecting or inserting connections, one at a time, and then routing them to completion.  It may require a lot of panning around and can possibly lead to a large amount of rerouting toward the end of dense designs. Sweep route one window at a time: take a look at the picture below. It shows one completely routed window of a design. The idea is to zoom in to a comfortable magnification and to route everything in that window. If a connection passes through the window on a diagonal, then drag it to a corner and ‗tack‘ it there because it has no business in the current window. If you did not turn off angle snap in User Preferences then you may have to override the snap behavior by holding down the Ctrl key while routing. For connections that pass orthogonally through the window use the same tactic but find an open channel in the window and route it through the window. Once the window is complete, pan to the next window and route that one. You should start in the densest region of the board and pan against the long axis of the board, I.E. if the board is mostly horizontal then pan vertically as your primary pan direction. This very powerful technique results in less rerouting and can identify serious trouble quicker than any other method. The default isolation gap between copper pour and other objects is 0.008‖ for standard 1oz copper clad and 0.013‖ for 2.5oz copper clad boards. This clearance may be increased on certain objects whose net spacing rule dictate a greater clearance, including the copper pour net itself. By specifying worst case spacing on grounds and voltages, copper pour can be safely used while guaranteeing adherence to standards and regulation bodies requirements such as Underwriter Labs (UL). Care must be taken when adding copper pour to congested areas so that pins are not isolated. Pins that belong to the same net have connection lines, or a ratsnest between them. The connection lines disappear when a continuous routed path is completed between the pins. The pins‘net is assigned to a plane layer and the pins hit the plane layer through a plated hole. The pins are contained in a copper pour region assigned to the same net. Because the display of the ratsnest is calculated on the fly, connections made with copper pour are assumed to be complete. However, this may not always be true. It is possible to isolate pins by carving up the copper pour region with too many other-net objects. Running a full DRC check on the board will detect possible isolations and the resulting error markers should be investigated carefully. The DRC check for isolations is pessimistic. First, It rasterizes the copper region at some minimum feature size so a pin might be flagged as isolated even though it may be connected by one or more slivers smaller than  0.004‖. Second, the isolation check is performed on a per-copper pour basis without regard to the rest of the net topology. This means that two pins inside a copper pour region of the same net may be reported as isolated even though they are connected by a different means such as another copper pour region on a different layer or even a plane layer.

• Design Changes: Design changes are an inevitable unpleasant fact so PCB123 has provided some tools to make incorporating design changes as simple and painless as possible. There are two methods for performing design changes. They are:

  Manual Changes: some types of changes are obvious. Adding a new component is as simple as clicking on the Add Component toolbar button and adding a connection is as simple as clicking on the Add Connection toolbar button. To delete a component just point at it and press the Del key on keyboard. To remove a pin from a net use the connection tool, right click on a pin, and select Disconnect Pin from the Context Menu. You can change the footprint for a component in Component Properties Dialog.

  Automatic ECO:  if your design is captured in a schematic then a very powerful tool available to you is the Automatic ECO feature. It will compare a design against a net list and perform all the necessary changes to the design to make it match the net list. It will do this in a highly optimal manner, disturbing the existing design as little as it can. It will even re-bind component footprints so if nothing changed on your schematic except a part type change then it will detect that in perform the update.

• Design Rule Checking: One of the last tasks want to perform on design is Run DRC. It is important enough that it is automatically run before you place an order. During the course of design, certain checks are done dynamically – mainly checks for shorts. Running a full DRC not only detects shorts but it also will detect opens and a range of fabrication rules such as pad annular ring size and drills too close together. Warnings may also be generated such as silkscreen on exposed copper areas such as pads. After DRC has been run you can cycle through the errors and resolve them. Pressing the ctrl+N   key on your keyboard will pan to the next error. When have reached the end of the error list, it will prompt to run another DRC to check if you cleared them all. 

• Object Editing: This section describes the operation of the commands used to edit objects in the PCB123 tool environment. 

• Changing line width: The simplest way to change the width of a line while drawing is to press the W key. This will invoke the Line Width Dialog. You can also RMB to get the context menu, which has a Change Line Width item.

 

• Add a component to the board:  To manually add a component to your design (as opposed to automatically with a net list) then the simplest way to do this is by clicking on the Add Component Button on the Insert Object Toolbar. You can also choose Insert/Component from the menu bar. Either way you will be presented with the Add Component Dialog that allows to graphically browse for a footprint that the component will use.

• Move a component: Depending on experience, there may be a tendency to point at a component, hold down the LMB and drag that component. Though this is allowed, a much easier way is to point at the component and LMB click and release. This attaches the component to cursor and allows to do such things as use the RMB for context commands. Click once to select it and begin moving and click again to release it where want.

• Rotate a component: Once have a component selected on your cursor the easiest way to rotate it is to press the ‘R‘ key on keyboard. Alternatively, while have the component on  cursor can RMB to display the context menu and then select the rotate command. Component rotation is always performed counter-clockwise. To edit the contents of a component, select a component, RMB to display the context dialog, and select the Edit Footprint command. This will invoke the Footprint Editor, which allows to graphically modify the component contents such as pins and outline data.

• Add a pin to the board If want to manually add a pin to design, then the simplest way to do this is by clicking on the Add Pin Button  on the Insert Object Toolbar. Insert/Pin from the menu bar. Once have selected this command, a default pin will be attached to cursor and there will be a Pin Context Pane in the left panel that allows to edit some of the more common pin properties.

• Move a pin Only board-level pins can be moved in a design. To move component pins, must edit the component in the Footprint Editor.

• Change a pin

• If  have one or more pins selected can press Alt+Enter on keyboard or alternatively RMB to display the context menu and select the Properties command to invoke the Pin Properties Dialog which allows to change any pin property.  

• Move a board outline

• To move an entire board outline just left click on it and drag, releasing the mouse button when have position the board outline where want.

• Add a connection between two pins To add a connection between two pins click on the Connection Tool  to  place the system in Add Connection Mode. Once in this mode simply click on the first pin want to add the connection between. After clicking on the first pin, will be rubber-banding a line while the system waits for to click on the other pin that completes the connection.

• If neither pin is tied to a net then a new, unique net name will be created for the connection. If one of the pins is tied to a net, then the connection and the other pin will inherit that net name. If both pins are tied to different nets then will be prompted to merge the nets together.

 

• Start routing from a pin

If there is already a ratline (connection) tied to a pin simply click on it to begin routing. If the pin is a through hole pin then you will be routing on the current layer. If the pin is an SMD pin then the route will begin on whatever surface layer the pin is on. Once you have begun routing you can continue to digitize new corners until the route is completed or you press the Esc key to stop routing. Alternatively, you can click on the FreeStyle Routing Tooland then click on a pad to start routing. The same features as above apply in this mode with the only difference being if the pin was not previously tied to a net then a new, unique net name will be created with the pin and the route tied to it. Start routing from another route You can start a new route from a previous on by clicking on the FreeStyle Routing Tooland then clicking on an existing route. The new route will inherit the net from the route you clicked on and you will be routing on the same layer as that route.

• Move a route segment

If you point at a route segment and hold down the left mouse button while dragging, the entire route segment will move with the cursor.

• Change the width of a route segment

You can only change the width of an individual route segment while you are routing by pressing the ‘W‘ key on your keyboard or RMB and selecting Width… from the context menu. To change the width of an existing route segment you must first click on that segment to get into Insert Corner mode and then press the ‘W‘key.

• Rename a component

you are new to PCB123 renaming a component may appear counter-intuitive at first because you may just point at a reference designator text object and attempt to change its name only to find that you can‘t. You must select the component object and change its name in the Component Properties Dialog. The text object is just a manifestation of a macro placeholder that inherits its value from the component reference designator. When you change the component name the text will automatically reflect the new name. When you rename a component for the first time a special attribute record is generated internally that remembers the original name. The original name will appear in a BOM Report so you can back-annotate your schematic if you so desire. This is also to facilitate the automatic back-annotation of schematics in the future.

Designing a board without a net list

• Depending upon the nature or complexity of the design, you may opt to skip a schematic altogether and start right in on the physical layout. In this case, you probably will not use or need a net list or a schematic editor. PCB123 can support you on these very simple designs as well. Just dive right in with physical layout. 

• About loading a Net list

If you have captured your design in a schematic tool then you should be able to create a net list that PCB123 can import. If you use the PCB123 schematics package to capture your design then any device use from the standard libraries will be mapped to a footprint in the layout software. Starting the layout with a net list opens a large array of benefits that you may or may not take advantage of. They include:

• Auto place – You can run the Auto place tool. This tool can be real handy just to gauge board density and get a feel for the overall flow of routing. 

• Placement Optimization – You can easily see what is connected to what as you place components on the board. In addition, the length of nets is continuously optimized as you move part around.

 

4.2 Making of Printed Circuit Board         

 

To generate own PCB's we need a computer, PC artwork software (e.g.pcb123 used in the project) and a printer. If this is a laser printer then so much the better as you can directly print the PCB pattern on to the oil

                              

                                               Figure 4.1 3D-view of PCB Layout

 

paper .  Very useful additions to such a computer system include a scanner and a photo processing package such as Adobe Photoshop or Paint Shop Pro. However, many photocopiers and laser printers also include the ability to do horizontal flips (and negatives of an artwork) in their operating menus and so the photo processing software may not be necessary.PCB layout for mobile bug  using   PCB  123  Whichever way you choose to generate the PCB track pattern, the end result must be a piece of special clay paper with a mirror image on its surface of the image

wish to produce on the PCB copper. The image produced by the toner on this paper must be very dense and black with NO pinholes. The special clay paper must be handled by its edges only, to avoid contaminating its  surface

 

                                                Figure 4.2 PCB Layout diagram for fabrication

 

with finger skin oils, which will ruin the adhesion of the plastic toner to the copper surface of the PCB. The PCB pattern is transferred to the copper by re-melting the finely ground PVC toner on the surface of the oil paper with a clothes iron so that it sticks to the copper. The paper behind the toner therefore has to be removed to allow chemical etching of the copper, and this is accomplished by a process of soaking and gentle rubbing. Standard A4 paper will not work because during printing, the finely ground PVC toner particles have been melted into the wood fibers which form the paper surface. When the paper backing is scrubbed away ,  just the toner protecting the copper surface, the wood fibers pulls some of the toner off the copper, completely destroying any etch protection. The paper which is used to produce photo quality prints on your inkjet printer is a very different animal to the paper normally used for text printing. This type of paper (oil paper) has very little wood fibred in it and these few fibers are used to form a central supporting core. The surface of this paper is made from pure very finely ground white china clay, and when viewed with a magnifying glass, appears totally smooth with the appearance of fine unglazed china. When this sort of paper is moistened and gently rubbed, the toner is released from the smooth clay surface without damage.

4.3 PCB Preparation

The surface of the copper must be absolutely clean and completely free of oils, oxides, stains and finger salts. This is achieved by firmly rubbing the surface of the copper using a small amount of detergent and a genuine Scotchbrite pad with a circular scrubbing motion. This will actually remove a very slight amount of copper, but don't worry because this is exactly the process. The appearance of the copper surface when this process is finished will be uniformly dull all over, with tens of thousands of fine circular scratches which form a 'key' on the copper surface to which the toner can bond. When this surface appearance has been achieved, the board surface is carefully rinsed off and then dried using a plain paper kitchen. Do not touch the board surface after it has been dried. If you do finger oils will destroy toner adhesion. The use of genuine Scotchbrite kitchen pads is highly recommended as they are flexible enough to reach to the bottom of the indentations created in the copper surface by the crises crossing patterns of glass fibers under the copper surface. Further, the real pads contain finely ground pumice, which really cuts through the surface contamination on the copper. In summary, it really doesn’t matter how you get the copper surface clean, but spotlessly clean it must be!! Those in the business of electroplating have a quick test for a clean metal surface, and this is the NO WATERBREAKS test. After the board has been cleaned and washed, the thin film of water remaining should entirely and smoothly cover the copper surface with no breaks visible in the film. If the copper surface is very badly contaminated with oil, I sometimes use a kitchen Scotchbrite pad together with Ajax cleanser (a mixture of ground pumice and wetting agents) to get the scrupulously clean surface needed. Lastly, whatever you use to dry the surface, make sure there are no traces of oil in it. If you have adhesion problems, it will be due to contamination of the copper surface.

4.3.1 Transferring the Image

To transfer the image, fold the paper around the PCB material so that no relative movement between the two is possible. The back of the paper is then ironed on a hard flat surface. The iron temperature is adjusted so that after about 20 seconds of ironing the back surface of the clay paper has been uniformly discolored to a light yellow. Typically the iron temperature setting used will be towards the upper end of scale (cotton or linen) and the iron is of course used dry. The clay paper surface should remain flat during ironing and particular attention should be paid to the corners of the PCB pattern with the iron tip. The paper/PCB assembly is then allowed to cool for about 5 minutes until it is near room temperature. (Do not throw the PCB/paper assembly into water while it is hot as this will destroy the toner/copper adhesion.) When the assembly has cooled, soak it in water for 5 minutes.

4.3.2 Removing the Paper, Etching, and Cleanup

When the paper/PCB is removed from the water it will be noticed that where there is no toner the paper has bubbled outward (which indicates good toner adhesion to the copper). Take a very soft nail or tooth brush, coat its surface with Velvet soap, and gently scrub the rear of the paper, keeping everything wet. The objective here is to reduce about 70% of the paper thickness to pulp but not to break through to the copper surface. The Velvet soap assists in wetting the junction between the clay backing and the toner and assuring its damage-free release. The last part of the backing is removed using the finger tips only with a gentle circular rubbing motion. Be patient and use only light pressure. If you have done everything correctly the undamaged toner track pattern should now appear on the surface of the copper. The PCB is then etched in one of the standard etching solutions such as 43% ferric chloride. In an unstirred etch tank, etch the board face downwards. This allows the chemical products of etching to fall away from the copper surface, exposing fresh copper and minimizing etch times. Damage to the toner resist can be prevented by drilling 3 or 4 holes in the waste areas of the PCB and fitting plastic computer motherboard stand-offs. It will be found that toner is an extraordinarily good resist and that it will tolerate brutal over etching. When etching is finished, the toner is removed with lacquer thinners or a hydrocarbon such as petrol.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CHAPTER 5

CONCLUSION AND FUTURE SCOPE

 

CONCLUSION

               The Mobile Bug designed will    frisking. This reduces lot of time wasted for checking each individual It covers a wide range of detection of frequencies between   800MHz  to  3GHz .The bug can be constructed .This pocket-size mobile transmission detector or sniffer can sense the presence of an activated mobile cell phone from a distance of a half meter. So it can be used to prevent use of mobile phones in examination halls, confidential rooms, etc. It is also useful for detecting the use of mobile phone.

It can be used to prevent use of mobile phones in examination halls, confidential rooms , etc. It is useful where the use of mobile phone is prohibited like petrol pumps and gas stations, historical places, religious places and court of laws. The prototype version has only limited range of half meters.

FUTURE SCOPE

          In the present design there is a limitation that its range is limited. But if a preamplifier stage using JFET or MOSFET transistor is used as an interface between the capacitor and IC, range can be increased. Trying to increase the detecting  range of mobile bug to few more meters for  observing  wide range of area. Secondly, in a particular case of an examination hall , it is not possible to identify the direction of  activated  phone .A special advancement has to be made to obtain the coordinates